Half adder

Defined as :
“A logic circuit for the addition of two, one- bit number is known as HALF ADDER“.
A and B are the two inputs(i.e. two ,one-bit binary numbers),and output is their addition( i.e. SUM with CARRY).

TRUTH TABLE for half adder is shown below,
when both the inputs are zero,sum will be zero .
when one of the input is 1,sum is 1 with no carry output.
And when both the inputs are 1,then sum is 0 and a carry is generated(.i.e c=1).

A  B SUM(S) CARRY(C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

k-map for the SUM output is below,

so the simplified expression will be, The SUM carried out above is similar to that of an Ex-OR operation.

Now the k-map for carry is,

& the simplified expression will be ,
Carry output is similar to that of an AND operation.

So the logic circuit for half adder will be the combination of EXOR gate and AND GATE ,which is shown below.

CIRCUIT DIAGRAM
Simplifying Boolean equation will produce the circuit ,

LOGIC EXPRESSION for SUM and CARRY is

LOGIC SYMBOL


NAND gate implementation of HALF ADDER circuit,


Total five NAND gates required to design half adder circuit given below.
similarly,with NOR gates
We need five NOR gates to design half adder,

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