# Flip flop

Introduction

• Basic digital memory circuit is known as flip flop.
• It is a basic memory element that can store one bit of information.
• It has two outputs(Q & Q’) complement to each other.
• It has two stable states known as 0 state and 1 state.
• It can be obtained by using NAND or NOR gates.

Fundamental circuit of flip flop

• Fundamental circuit of flip flop consist of  two inverter gates ( gate 1 & gate 2), here NAND GATES are used as inverters.
The output of gate1 (Q) is connected to input of gate2 (B) and output of gate 2 (Q’) is connected to  input of gate1 (A).
• Now lets assume output of gate1 (Q) to be 1, since it is connected to input of gate2 (B), so gate2 input (B) will be 1.Therefore ,output of gate2 (Q’) becomes 0. It makes input of gate1 (A) is equal to 0. Thus output of gate1 (Q) will be 1,which confirms our assumption.
• Similarly, when we assume output of gate1 (Q) equal to 0,then it makes input to gate2 (B) equal to 0.Then we get output of gate2 (Q’) equal to 1,which makes input to gate1 (A) equal to 1,again in result we get ouput at gate1 (Q) equal to 0. Which again confirms our assumption.

from all of this,what we concluded is :

point 1 : The output are  always complementary i. e. Q and Q’

point 2 : Circuit has two stable states ( 1 state and 0 state ).1 state is also known as set state and 0 state is known as reset state.

point 3 : If circuit is in 1 state ,it continues to be in that state.In the same way,if it is in 0 state then it will remain in that state.This property what we called is memory  i.e. It can stores one bit of information.
This circuit is also known as latch since information is latched in it i.e. locked in it. In this circuit, we can not enter desired information.Since when power is ON ,the circuit switches to one of the state ,either to 1 state or 0 state ,we can not predict it.
We overcome from  this by replacing inverters with 2-input NAND gates. One of the input terminal of NAND gate can be used to enter desired information which we want to enter .Circuit is shown below ,two additional inverters is added in this gate 3 and gate 4.

Now here,
point 1 : If we enter inputs  S=1 , R=0
output of gate3 will become 0 and output of gate4 will become 1. This will make final output Q= 1 and Q’ =0. It is set state, when output Q is 1.

point 2 : If S=0 ,R=1
the output at gate3 will be 1 and output at gate4 is 0.This will make final output Q= 0 and Q’=1.This is reset state Q=0.

So we can enter desired value in the latch.

point 3 : when we put inputs ,S=R=0
circuit behaves as latch ,this means output will have the same value what they previously having i.e. output equal to previous state. For e.g. if previous output is 0       i .e. Q = 0,then after that  S and R becomes 0 (S=R=0), it will not change the output.The output will remain 0. The output remains unaltered. Similarly ,if Q=1,after that inputs S and R becomes 0,it will not change the output.The output will remain 1 only.

point 4 : when S=R=1
In this condition , gate3 and gate4 output becomes 0 , which will make both the output (Q and Q’) equal to 1.which is not allowed .Therefore ,this condition is not allowed or prohibited.

This circuit is known as S R FLIP FLOP.